Saturday 25 May 2019

digital logic - How to get a FPGA design that will definitely work on actual hardware


I have just started learning digital logic design with FPGA's, and have been building a lot of projects. Most of the times (since I am kind of a noob), I have a design that simulates perfectly (Behavioural simulation) but does not synthesize properly.


So, my question is "what are the design steps that I can incorporate in my workflow, that will ensure that I have a working design that will work right on my FPGA ?"



I have two main areas where I expect advise, but this is absolutely based on a very narrow viewpoint of mine as a beginner, and more are welcome :



  • What all steps (viewing RTL schematic, post synthesis simulation, ...) should I undertake learning for the best practice.

  • What all things should I keep in mind while designing my logic (say FSM's or sequential circuits) to avoid any unexpected results.


I am using a Xilinx Spartan 6 FPGA, and Xilinx ISE Design suite for my work.




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