I can't seem to wrap my head around the math.
Assuming I want a 640x480x256
VGA signal, and I had an FPGA or fast micro-controller to drive it, would 55ns
be able to handle it?
Meaning each byte of the 8-bit memory would translate to one pixel. Also assuming my R-2R ladder was setup to something like RRRGGBBB
.
I have a very specific reason to use DIP SRAM. I can find speeds down to about 15ns
but small sizes. The 512k
I want to buy tops out at 55ns
.
If someone could give me examples of how the bandwidth is calculated, it might help me decide to use the 512k or maybe do something different with multiple 15ns chips.
Thanks!
Answer
640x480x60Hz uses a 25 MHz pixel clock so you'd need 1 byte every 40 ns (for 73 % of the time).
You also want to be able to write display data to your RAM so let's assume we want two RAM byte accesses in that 40 ns: one to read and display a pixel, one to R/W display data.
So you can either buy faster RAM or wider RAM. A 32-bit wide RAM using 55 ns chips could serve up four bytes in one 60 ns read and they'd last 160 ns.
This illustrates the arithmetic, you can explore the permutations further. If you're using an FPGA, you can do some clever prefetching stuff to burst-read multiple dwords and get more R/W slots in between them.
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