I always imagined the photolithographic microchip manufacturing to be a 2D layer creation process without layering, thus creating a topological problem for circuitry when you have some \$K_{3,3}\$ or \$K_5\$ in it, which would certainly be the case for any non-trivial design.
And there are papers out there talking about producing "3D" chips with multiple layers to save space, thereby adding to the confusion.
Yeah, that's sad, but that is what I learned in school, a bunch of mysterious riddles. It's no wonder people start conspiracy theories about aliens catering those technologies to us.
So how can we build complex processors and chips just using a 2D topology ?
Answer
It turns out that there are layers, but people sometimes skip those when talking about how a microchip works.
The process that introduces layers is called Back end of line, or BEOL.
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It basically works like this:
- Create the 2D chip layer using photolithography
- Apply an insulating layer
- Drill holes into that layer
- Apply a conducting layer, also filling the created holes and create circuit paths or interconnects
- Repeat those steps as often as needed and your manufacturing process and maybe other considerations such as thermal design allows
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