pcb design - Distributing Ground and Clock Between ADC and FPGA on Separate PCBs

This question is in reference to my previous question where some suggestions were made that went somewhat off-topic.

Basically I have a built a system with an FPGA and very sensitive ADC (sensitive to picoamp currents) which is working well, but now it has to be separated into two PCBs.

Major questions are

1. How to properly share GND between the two boards in order to minimize ADC noise/error at all costs?


2. How to properly buffer the CLK and serial signals in and out of the ADC?

My proposed solution:

Concerns I'm having:

• I know the ribbon should have GND in between each signal (since some are 40MHz) but should GND be connected to both planes on either side?


• It was suggested to buffer the ADC I/O so that the ADC doesn't have to drive a lot of current, but where do the buffers get their power and ground from?



• Here I have signals traveling over the edges of ground planes, which I've heard defeats the purpose of having a ground plane.


• Since the PCBs are already getting a GND connection at the power supply, doesn't also having GND in the ribbon create a loop?

Answer

Using isolators is the most straight forward way to couple boards like this while avoiding grounding and noise headaches.

For an isolated design to function, you need isolating buffers for all the digital input and outputs as well as an isolated power supply, although the later can be ignored if the power ground acts as the "star point" for your daughter board and you do not require isolation on the sensor part (e.g. a 'floating adc').

Conceptually this can be imagined by the following diagram

^{simulate this circuit – Schematic created using CircuitLab}