I have read at numerous places that NAND gate is preferred over NOR gate in industry. The reasons given online say:
NAND has lesser delay than Nor due to the NAND PMOS (size 2 and in parallel) when compared to NOR PMOS (size 4 in series).
According to my understanding delay would be the same. This is how I think it works:
- Absolute delay (Dabs) = t(gh+p)
- g=logical effort
- h=electrical effort
- p=parasitic delay
- t=delay unit which is technology constant
For NAND and NOR gate (gh+p) comes out to be (Cout/3 + 2). Also t is same for both. Then delay should be the same right?
Answer
1. NAND offers less delay.
As you were saying, the equation for delay is $$Delay = t(gh+p)$$ But the logical effort \$g\$ for NAND is less than that of NOR. Consider the figure showing 2 input CMOS NAND and NOR gate. The number against each transistor is a measure of size and hence capacitance. 
The logical effort can be calculated as \$g = C_{in}/3\$. Which gives
- \$g = 4/3\$ for 2 input NAND and \$g = \frac{n+2}{3}\$ for n input NAND gate
- \$g = 5/3\$ for 2 input NOR and \$g = \frac{2n+1}{3}\$ for n input NOR gate
- refer wiki for table.
\$h=1\$ for a gate (NAND or NOR) driving the same gate and \$p=2\$ for both NAND and NOR. Hence NAND has lesser delay when compared with NOR.
EDIT: I have two more points to but and I am not 100% sure about the last point.
2. NOR occupies more area.
Adding the sizes of transistors in figure, it is clear that size of NOR is greater than that of NAND. And this difference in size will increase as the number of inputs are increased.
NOR gate will occupy more silicon area than NAND gate.
3. NAND uses transistors of similar sizes.
Considering the figure again, all the transistors in NAND gate have equal size where as NOR gates don't. Which reduces manufacturing cost of NAND gate. When considering gates with more inputs, NOR gates requires transistors of 2 different sizes whose size difference is more when comparing with NAND gates.
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