I've gone through the complete datasheet, searched SE and on google, but I cant seem to find this information:
Whats the output Voltage of QA..QH just after power-up when G (Output enable) is pulled low, but no data have been clocked into the shift register?
Answer
Unless otherwise stated, the outputs will be indeterminate. i.e. any output may be 0 or 1 which appears to be the case here.
This is why the SCLR pin (shift register clear) is provided, so that the outputs may be put into a known state which should be done prior to enabling the outputs.
Alternatively, a valid pattern may be shifted in to the device, but in either case this is normally done prior to the outputs being enabled (unless your circuit does not care).
This is normal for many parts.
In response to Crowie's comment, why are the outputs indeterminate is indeed a far more interesting question:
The output stage of a D flip flop is simply an RS latch as shown:
At power up, the two outputs start to rise, but at different rates and assume the inputs are also pulled to the positive power rail.
If the Q output rises faster then the lower gate will have two highs first, taking the \$ \overline Q \$ solidly low; this locks out the \$ \overline S\$ input and maintains this state until \$ \overline R\$ is pulled low.
Which of the outputs changes more quickly determines the initial output state, but for a given device it is simply unknowable and therefore we call the outputs at power-up indeterminate.
For completeness, here is the venerable 7474 clocked D flip flop:
With the exception of the PRE (preset) input, this is likely a close approximation to the latches in the '595.
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