fpga - vhdl synthesis optimization: counters in statemachines

I have a general question about the efficiency of a synthesizable state machine.

The first version uses the same counter for each state. The second uses one own counter for each state. Which version of the two is more efficient (logic area, speed...)??

How much area of the FPGA is occupied by the routing of the count1 signal when i use the same counter for each state. Is it better to user one counter for each state??

I'hope somebody with more experience can explain which solution is the best (maybe a third version) and why.

Thank you!

Kind Regards,

Oliver

-- 1. Version ===============================================================

signal count1: integer range 0 to 1000 := 1000;  
type mystates is (s1, s2, s3, s4);  
signal mymode: mystates := s1;  

BEGIN  


MyProcess: process(clk)  

BEGIN  

    IF (clk'event and clk = '1') THEN  

        case mymode is  
        when s1 =>   
            If (count1 = 0) then  

            mymode <= s2;
            count1 <= 555;
            -- (stuff)
            else  
            count1 <= count1 - 1;  
            end if;  
        when s2 => 
            If (count1 = 0) then  
            mymode <= s3;
            count1 <= 666;

            -- (stuff)
            else  
            count1 <= count1 - 1;  
            end if; 
        when s3 => 
            If (count1 = 0) then  
            mymode <= s4;
            count1 <= 784;
            -- (stuff)
            else  

            count1 <= count1 - 1;  
            end if; 
        when s4 =>  
            If (count1 = 0) then  
            mymode <= s1;
            count1 <= 1000;
            -- (stuff)
            else  
            count1 <= count1 - 1;  
            end if; 

        when others =>  
            Null;  
        end case;  

    END IF;

end process;

-- 2. Version ===============================================================

signal count1, count2, count3, count4: integer range 0 to 1000 := 1000;  

type mystates is (s1, s2, s3, s4);  
signal mymode: mystates := s1;  

BEGIN  

MyProcess: process(clk)  

BEGIN  

    IF (clk'event and clk = '1') THEN  


        case mymode is  
        when s1 =>   
            If (count1 = 0) then  
            mymode <= s2;
            count1 <= 555;
            -- (stuff)
            else  
            count1 <= count1 - 1;  
            end if;  

        when s2 => 
            If (count2 = 0) then  
            mymode <= s3;
            count2 <= 666;
            -- (stuff)
            else  
            count2 <= count2 - 1;  
            end if; 
        when s3 => 
            If (count3 = 0) then  

            mymode <= s4;
            count3 <= 784;
            -- (stuff)
            else  
            count3 <= count3 - 1;  
            end if; 
        when s4 =>  
            If (count4 = 0) then  
            mymode <= s1;
            count4 <= 1000;

            -- (stuff)
            else  
            count4 <= count4 - 1;  
            end if; 
        when others =>  
            Null;  
        end case;  

    END IF;


end process;