I need to analyze the power consumption using RTL Compiler based on the VCD file generated by ModelSim. I have two files:
gcm.v (This is the main circuit. Module name is "gcm")
tb.v (This is the testbench. Module name is "tb", and "gcm" is instantiated as "gcm_tb")
The command to generate vcd file is in tb.v as below:
$dumpfile ("testb. vcd"); $dumpvars (1, testbench.gcm_tb);
Here is my script for RTL compiler:
set_attribute lib_search_path /opt/cadence/local/FreePDK45/osu_soc/lib/files
set_attribute library {gscl45nm.lib}
read_hdl -v2001 tb.v
elaborate
read_vcd -vcd_module gcm_tb -module gcm -static testb.\ vcd
synthesize -to_mapped
write -mapped > gcm_synth.v
report power -tcf_summary > power.txt
exit
RTL compiler gives me the same power numbers with and without the VCD file. Here is my power summary in power.txt:
============================================================
Generated by: Encounter(r) RTL Compiler v07.10-p004_1
Generated on: Mar 28 2013 03:47:17 PM
Module: ccm
Technology library: gscl45nm
Operating conditions: typical (balanced_tree)
Wireload mode: enclosed
============================================================
Leakage Dynamic Total
Instance Cells Power(nW) Power(nW) Power(nW)
---------------------------------------------------
ccm 2963 71474.787 535247.155 606721.942
add_147_11 127 6038.327 11984.664 18022.991
a_aes 0 0.000 19505.200 19505.200
e_aes 0 0.000 26450.600 26450.600
-------------------------------------------------------
Total nets in design : 3865 (100.00%)
Nets asserted : 0 (0.00%)
Nets computed : 3862 (99.92%)
Default nets : 0 (0.00%)
Clock nets : 0 (0.00%)
Constant nets : 3 (0.08%)
Net does not have TCF asserted : 3865 (100.00%)
-------------------------------------------------------
I see the nets asserted is 0. Is this the reason why the power consumption did not change?
Thank you!
Answer
$dumpvars (1, testbench.gcm_tb);
is your problem. To get all the lower-level signals you need $dumpvars (0, testbench.gcm_tb);
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