Sunday, 15 May 2016

Common drain JFET output resistance "problem"


The output resistance of small signal model for common drain JFET amplifier equals 1gm||Rds(on)RS

and since Rds(on)=1gm
we can also write this formula as $\frac{1}{g_m} \parallel \frac{1}{g_m} \parallel R_\text{S}$ right?


Which could be derived to ROUT=1gm/2RS

right?


enter image description here



Answer



$g_m$ is a transistor transconductance. In saturation region we viewing the transistor (FET) as a voltage controlled current source.

Vin is a input voltage and the output is a current, hence $g_m=\frac{Io}{V_{in}}$


Hence, for the FET $g_m$ is equal to $gm = \frac{dI_d}{dV_{gs}}$ (slope of the Id = f(Vgs) function)


In saturation region the Drain terminal behaviour just like an current source controlled via $V_{gs}$ voltage. And this is why you see the voltage controlled $(V_{gs})$ current source $I_d = g_mV_{gs}$ in the small signal equivalent circuit. Look at the answer given by KingDuken.


But this "drain" current source is not ideal. For the ideal current source the output current (drain current $I_D$) does not depend upon the voltage across it ($V_{ds}$). But in the real transistor $V_{ds}$ voltage due to channel length modulation will have small effect on the drain current.


And to "model" this effect (to represent channel length modulation on the small-signal equivalent circuit), we add a resistor $r_o$ parallel to the drain current source.


enter image description here


enter image description here


As you can see $r_o \approx \frac{1}{\lambda I_D}$ represent variation of $I_D$ with $V_{DS}$.


And $R_{ds(on)}$ is a FET resistance in the triode region when FET is full-on and $V_{ds}$ is very low $V_{ds}<<(V_{gs} - V_{th})$.


We can estimate the lambda value if we solve this set of equations:



Id1=K(VgsVth)2(1+λVds1)


Id2=K(VgsVth)2(1+λVds2)


Id1Id2=Kλ(Vds1Vds2)(VgsVth)2


Use the above to calculate $\lambda$


λ=Id1Id2K(Vds1Vds2)(VgsVth)2


Or this one


λ=Id2Id1Id1Vds2Id2Vds1


Additional we can find $K$ factor


K=Id1Vds2Id2Vds1(Vds2Vds2)(VgsVth)2


enter image description here



But we never do this type of calculation when designing circuit using a discrete FET's.


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