fpga - What is clock skew, and why can it be negative?

My HDL compiler (Quartus II) generates timing reports. In it, the nodes have "clock skew" column. The only definition of clock skew I found is in the TimeQuest documentation (see page 7-24):

To manually specify clock uncertainty, or skew, for clock-to-clock transfers, use the set_clock_uncertainty command.

So if skew is "uncertainty", why are some of my clock skews negative (e.g. -0.048)? What exactly is clock skew?

Answer

From Wikipedia:

In a synchronous circuit clock skew (\$T_{Skew}\$) is the difference in the arrival time between two sequentially-adjacent registers. Given two sequentially-adjacent registers \$R_i\$ and \$R_j\$ with clock arrival times at register clock pins as \$T_{Ci}\$ and \$T_{Cj}\$ respectively, then clock skew can be defined as:

$$T_{Skew i,j} = T_{Ci} - T_{Cj}$$

Clock skew can be positive or negative. If the clock signals are in complete synchronicity, then the clock skew observed at these registers is zero.

So the amount of clock skew at one register is relative to another register. Since it's relative, it can be positive or negative.

Some illustrations:

Take for example an intraclock transfer as defined in the TimeQuest document you provided:

Intraclock transfers occur when the register-to-register transfer takes place in the core of the device and the source and destination clocks come from the same PLL output pin or clock port.

So if the destination register is physically closer to clock generation circuitry, then the clock will probably arrive at the destination register before it arrives at the source register, resulting in a leading clock skew which is actually positive. If the destination register received the edge of the clock after the source register, the clock skew would be lagging or negative.

Said another way, clock skew is the uncertainty about how closely together in time a clock edge will reach two separate registers given in units of time with respect to a source register in an register-to-register transfer.

Expanding that difintion to include inter -clock transfers and setup and hold times gets a bit messy. So it's probably easier to think of it as "how synchronous" an edge or a hold time is between two registers. We tend to think of "synchronous" as "occurring at the same time". But things rarely occur at absolutely exactly the same time. So we need to put a tolerance on that time. And tolerances are often stated in terms of positive and negative (i.e. ±).