Hysteresis control disadvantages?

This article gives 2 main disadvantages:

1. Variable frequency



2. Requires ESR on the output cap

Is variable frequency a big of a deal? Why would synchronization matters for a converter? And why are high ESR necessary for it to work? What I'm missing here?

I ask this because I've been working on a boost converter with hysteresis control as a Uni project, and I've found very little resources or interest - giving me the impression that either the solution is known and considered bad, or that is unknown but not worthy of research.

Is Hysteresis control undesirable? What makes it so?

Answer

Is variable-frequency a big deal? Imagine you are designing an EKG machine for testing patient's hearts. Those work by measuring tiny electrical pulses generated by the body. Now imagine the power supply had one filtering cap, designed to block 99.99% of 120Hz mains hum. A capacitor's ESR fundamentally varies with frequency, so while this cap may work very well to block 120Hz hum, it may do little to block 80kHz. So using a hysteretic supply, with it's widely-changing frequency, could switch at 80kHz, and result in a "ripple" of power which goes right past the filtering cap. The end result is a "blip" on the screen where there shouldn't be one. This is why voltage-mode PWM is used - the switching frequency is precise and known, so pulses at that frequency can be blocked.

Why does synchronization matter for a converter? For a single converter, there isn't anything to synchronize it to... unless controlled by any kind of clock-driven device, such as a CPU or microcontroller. But for multiple converters, synchronization is often necessary. Consider a modern PC motherboard's CPU and Voltage Regulation Module (VRM). The motherboard is supplied 3.3v at 40A, but the CPU needs 1.2v at 90A. So the VRM bucks 3.3v down to 1.2v. But no single device can switch 100A, so instead, three to six devices "take turns" bucking this down. Now if they all worked simultaneously, the output would be very noisy, as they all switch on and off at the exact same time. Instead, they are switched in sequence, or phase, which greatly reduces noise. To switch these in phase, requires them to be synchronized.

Why is high-ESR required for hysteretic control to work? My initial thought was, if there were zero ESR, then the output voltage would mirror the hysteresis of the comparator as a minimum. i.e., tons of ripple at who-knows-what frequency (dependent on capacitance value also.) Throw a power inductor in there, and this ripple could tend to oscillate or at least degrade stabilization. Perhaps I'll simulate it in LTSpice and see what that does.

Is hysteresis control undesirable? I wouldn't say so. Uncommon or minimalistic perhaps. PWM has been around for a long time and works reliably, but is more complex and expensive. Hysteretic is less expensivee, but frequency-variant. I think it's a great topic!

Here's an informative link about adding hysteresis to comparators.

EDIT: Here is the LTspice simulation results and .asc file contents. The LT1011 Comparator was used simply because it is a default component of the simulation package. Now there are many aspects of this design which are undesirable and prone to spurious behavior, so it is presented for informational purposes only. Click to open full-size.

This simulation result is highly dependent on the parasitic constituents of the circuit, and since no simulator includes all parasitics, I doubt it would physically work as robustly as shown. The MOSFET gates are capacitive, and the comparator is driving them directly - it is doubtful they would really switch as quickly and cleanly as simulated. It could even oscillate wildly - it has not been tested. But in this configuration, the output is remarkably stable for loads of 1mA, 100mA, 1, 2, 3A with good transient response. The output ripple (after filtering) is less than +/-5mV in all cases. The output filter does introduce a fairly nasty 3.5v spike when dumping the 3A load however.

If I were going to test this and use it for say, a microcontroller, I'd probably set vref to 3.8v or so and use a LDO regulator after it to ensure no spikes come through. Note that with some other comparators tested, overshoot at start-up was a real issue also, with vout going as high as 4.5v for a few milliseconds.

Sure, the start-up overshoot could be suppressed, and the output clamped with a crowbar circuit... but then for all this added complexity, why not just use a PWM drive instead? In any case, happy experimenting.

Version 4
SHEET 1 2328 692
WIRE 432 0 384 0
WIRE 544 0 496 0

WIRE 80 16 80 0
WIRE 384 64 384 0
WIRE 384 64 272 64
WIRE 416 64 384 64
WIRE 544 64 544 0
WIRE 544 64 512 64
WIRE 592 64 544 64
WIRE 752 64 592 64
WIRE 1024 64 832 64
WIRE 1120 64 1024 64

WIRE 80 112 80 96
WIRE 800 144 768 144
WIRE 896 144 880 144
WIRE 1120 144 1120 64
WIRE 80 256 80 240
WIRE 880 272 880 240
WIRE 880 272 864 272
WIRE 432 288 432 112
WIRE 672 288 432 288
WIRE 768 288 768 144

WIRE 768 288 672 288
WIRE 784 288 768 288
WIRE 896 304 896 144
WIRE 896 304 864 304
WIRE 912 304 896 304
WIRE 1024 304 1024 64
WIRE 1024 304 992 304
WIRE 1120 304 1120 224
WIRE 1200 304 1120 304
WIRE 1328 304 1200 304

WIRE 592 320 592 64
WIRE 656 320 592 320
WIRE 592 336 592 320
WIRE 1328 336 1328 304
WIRE 80 352 80 336
WIRE 272 352 272 64
WIRE 656 352 656 320
WIRE 896 352 896 304
WIRE 1024 352 1024 304
WIRE 1200 352 1200 304

WIRE 832 400 832 336
WIRE 848 400 848 336
WIRE 848 400 832 400
WIRE 432 416 432 288
WIRE 544 416 432 416
WIRE 592 448 592 432
WIRE 656 448 656 416
WIRE 656 448 592 448
WIRE 272 464 272 416
WIRE 592 464 592 448

WIRE 832 464 832 400
WIRE 896 464 896 432
WIRE 1024 464 1024 416
WIRE 1200 464 1200 416
WIRE 1328 464 1328 416
WIRE 80 512 80 496
WIRE 80 608 80 592
FLAG 832 240 Vcc
FLAG 832 464 0
FLAG 1024 464 0

FLAG 1120 64 Vout
FLAG 672 288 Vsw
FLAG 80 352 0
FLAG 80 240 Vcc
FLAG 592 464 0
FLAG 272 64 Vcc
FLAG 272 464 0
FLAG 80 112 0
FLAG 80 0 Vref
FLAG 880 240 Vref

FLAG 896 464 0
FLAG 80 608 0
FLAG 80 496 V3
FLAG 1328 304 VoutF
FLAG 1328 464 0
FLAG 1200 464 0
SYMBOL res 1008 288 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R1

SYMATTR Value {Ra}
SYMBOL res 880 336 R0
SYMATTR InstName R2
SYMATTR Value {Rb}
SYMBOL res 896 128 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R3
SYMATTR Value {Rc}
SYMBOL cap 1008 352 R0

WINDOW 39 17 161 Left 2
SYMATTR SpiceLine V=35 Irms=5 Rser=200m Lser=1n Rpar=1MEG Cpar=1p
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SYMBOL res 1312 320 R0
SYMATTR InstName Rload
SYMATTR Value R=V(V3)
SYMBOL ind2 848 80 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 4 56 VBottom 2

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SYMATTR Value 25µ
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SYMBOL voltage 80 240 R0
WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
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WINDOW 0 -35 60 Left 2
WINDOW 3 -117 101 Left 2
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SYMATTR Value BSC360N15NS3
SYMBOL pmos 512 112 M270
WINDOW 0 -14 68 VLeft 2
WINDOW 3 -40 66 VLeft 2
SYMATTR InstName M1
SYMATTR Value Si7113DN

SYMBOL cap 256 352 R0
WINDOW 39 -9 161 Left 2
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WINDOW 123 0 0 Left 2
WINDOW 39 24 124 Left 2
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WINDOW 123 0 0 Left 2
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SYMBOL diode 640 416 M180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D1
SYMATTR Value RF101L4S

SYMBOL diode 496 16 M270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
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SYMATTR Value RF101L4S
SYMBOL cap 1184 352 R0
WINDOW 39 4 209 Left 2
SYMATTR InstName C3
SYMATTR Value 2200µ
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SYMBOL ind2 1104 240 M180
WINDOW 0 36 80 Left 2
WINDOW 3 36 40 Left 2
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SYMATTR Value 91n
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SYMATTR SpiceLine Ipk=14.5 Rser=0.0028 Rpar=338 Cpar=1.83p mfg="Wurth Elektronik" pn="7448510091 WE-DCT SH"
SYMBOL Comparators\\LT1011 832 288 M0
SYMATTR InstName U1
TEXT 984 512 Left 2 ;C2:

TEXT 208 512 Left 2 ;C1:
TEXT 1304 224 Left 2 !.tran 24m startup uic
TEXT 1216 -8 Left 2 !.params Vhb = 25mV  Vth = 3.30v  IR3 = 500uA\n.params Vcc = 5.00v  Vref = 3.30v\n.params Rc=min(Vref/IR3,(Vcc-Vref)/IR3)\n.params Ra=Rc*(Vhb/Vcc)\n.params Rb=1/((Vth/(Vref*Ra))-(1/Ra)-(1/Rc))
TEXT 640 -48 Left 2 ;5v to 3.3v buck converter - rough\nhysteretic control simulation
TEXT 1144 560 Left 2 ;C3:
TEXT 1456 312 Left 2 ;= 3.3k to 4ms (1mA)\n   33 to 8ms (100mA)\n   3.3 to 12ms (1A)\n   1.66 to 16ms (2A)\n   1.10 to 20ms (3A)\n   3.3k to 24ms (1mA)