bjt - Transistor rating with capacitive load

Considering the following circuit, how do I reliably protect the transistor Q1 from exceeding the collector current rating:

^{simulate this circuit – Schematic created using CircuitLab}

This is supposed to be a driving circuit for a PMOS with a delay to keep the PMOS off for a minimum amount of time after the OC input has been deasserted. The exactness of the time delay is not too critical but should be around 20ms minimum.

Answer

Treat this as an energy/power problem.

Capacitor C1 holds a certain amount of energy when fully charged: 100nF @ 36V (worst-case) is 65 µJ. This energy will be dissipated in Q1 whenever you discharge C1.

Clearly, any single operation will not endanger Q1. The question then becomes how frequently can you do this before the power dissipation (energy per time) becomes too large. For example, if you do this 1000 times a second, the dissipation becomes 1000 × 65 µJ/sec, or 65 mW. This would be getting into an area where you'd need to pay attention to the limit for a small-signal transistor with no heatsink.

However, given that the charging time constant is about 13 ms, I'm guessing that you're not going to be doing this more than about 10×/sec., so there should be no problem at all.

Looking at it another way, the maximum power that the combination of R2 and R3 can deliver to the Q1-C1 combination is (36V/2)²/132kΩ, which is just 2.5 mW — well within the capability of even a tiny transistor.

One other note: I'm not sure what you're trying to achieve overall, but be aware that the time delay of this circuit is very dependent on the supply voltage. At lower voltages, the delay will be significantly shortened. A better circuit:

^{simulate this circuit – Schematic created using CircuitLab}

This gives the general idea; the resistor values might need to be tweaked in order to get it to operate correctly over the full supply range. The key concept is that the node marked "Vref" tracks the supply voltage. Whenever the base of Q2 is greater than the base of Q3, Q4 is switched on; otherwise Q4 is switched off. C1 will charge to V_supply/2 in a fixed amount of time regardless of the actual supply voltage; this is the same basic principle used in the (in)famous 555 timer chip.

R11 is optional; it adds a tiny amount of hysteresis (positive feedback) — about 30 mV. This gives the output a better "snap action" that will minimize the time that the PMOS spends in transition.

Another thing I just noticed: I'm guessing that the source of your PMOS is connected to the power bus — are you sure it can withstand a V_GS of –36V?