hdl - Asynchronous reset in verilog

I am new to verilog and having a bit of trouble getting along with it.

I read about asynchronous and synchronous reset and i think i got hold of it but while implementing the same with verilog i am not able to understand a line of code which i saw on this website.

In the asynchronous reset code why are we using the always @ (posedge clk or posedge reset) instead of using always @ (posedge clk ).

I mean how are the two lines of code able to differentiate which is asynchronous and which is synchronous?

Answer

always @ ( signal 1, signal 2......) is a construct used in behavioural modelling.

The code which is present in the block following this construct will run only when any of the signals in the sensitivity list viz signal 1, signal 2... changes.

If you put only posedge clock in the list, the code will run only when there is a positive clock edge and not otherwise. You can use this to create clocked circuits which respond to no other signals but clock. For synchronous reset, then you will write

always @ ( posedge clock)
begin
if (reset)  //Do something
else     //Do something else
end

For your case, you want asynchronous reset. Asynchronous reset means that your circuit should reset whenever reset signal is active 'Irrespective' of clock. Naturally, this should be included in the sensitivity list.

always @ (posedge clk, negedge reset_n)
begin
if ( 'reset_n) //Then reset (active low).
else  // Do something else
end