clock - Counter in verilog

i want to make a counter that increases by the value of its inputs, but i did the testbench and the output is undetermined, xxxx. Can someone tell me if there is something wrong in this code?

    //Count

 module count(clk, 

 rst, val, coin



 );
//Declaración entradas y salidas

 input  clk, rst;
 input  [3:0] coin;
 output [3:0] val;

 reg [3:0] val;  
 reg [3:0] nval; 



 always @(posedge clk, negedge rst)
      if(rst == 0) val <= 4'b0000;
      else val <= nval;

    always @(val)
      nval <= val + coin ;
  endmodule