rf - Circular polarized micro-strip patch antenna

Circular/ Elliptical patch antenna design after a bit more research I realized what my mistake was, after a user pointed it out. As such my new post.

I have come across a CIRCULAR POLARIZED PATCH ANTENNA DESIGN (FINALLY!). Which is shown below. However, as you can see there is very little data that is shown on how to exactly construct such an antenna. My frequency is 915MHz, input impedance is 50 ohm.

My questions are (i.e. what are the equations?):

1. 
   

   The patch design is easy as I know of many resources that can assist me. But how do you calculate the width of the microstrip feed?

   
   


2. 
   

   How do you calculate the position of where the microstrip intercepts the patch antenna?

   
   



3. 
   

   How do you calculate the exact position of where the second feed line braches of the main feed line to form the 90degree out of phase feed line?

   
   

power supply - Specifying relay for breaking injection molding control circuit

I have an application which requires me to break a 24v signal running with low current (60ma being the absolute max). The signal stays on allowing a large hydraulic motor to close a mold with great force. If an obstruction is in the way, it will damage the mold when the hydraulics are activated. The goal is to use a PIC advanced 8 bit microcontroller running at 5v to sense a condition when there is an obstruction and signal the relay to open. My problem is finding the proper normally closed relay and determine how much response time is needed. It would be helpful if the relay could also work of 5 volt power rail and not exceed 0.5 amps of current to open.

Sadly the relay will be need to be placed inside the injection machine and will need to work in a normally closed manner because the object sensing device is only used on one job and will not always be set up to due to space constraints. The object detection system is a vision system to sense plastic parts that get stuck once in a while. It uses a Webcam hooked to a pc that sends a uart packet to the pic to trigger the relay. Currently the injection molding job operates without any protection so fail safe isn't the primary concern. I want to use the pic at 5 volts because I can easily use one DC power rail for the both energizing the relay and powering the pic. I don't have microcontroller experience aside from pic advanced 8 bit running xc8.

operational amplifier - Understanding op-amp circuits with extra capacitors in the feedback path

When looking at circuits like this one

circuit http://dt.prohosting.com/hacks/what1.gif

I often find (see U6-A in linked schematic) extra capacitors in the pF range slapped in parallel with the feedback resistors, although the op-amp has a buffering or gain function:

^{simulate this circuit – Schematic created using CircuitLab}

Doesn't that make it a low-pass filter instead? Is it supposed to filter out high frequencies or what other role does it play?

Answer

I'll do the circuit analysis.

This is an inverting amplifier with a gain of $$ |A_V| = \left| \frac{R_1 || -\frac{j}{\omega C}}{R_2}\right| = \left| \frac{R_1 / R_2 }{1 + j \omega R_1 C} \right| = \frac{R_1 / R_2 }{\sqrt{1 + (\omega R_1 C)^2}} $$ which gives you all of the information you need:

• At low frequencies (\$ \omega \approx 0\$), the gain is $$ |A_V| = \frac{R_1}{R_2} $$ so the DC gain of this amplifier is the same as it was without the capacitor.


• At high frequencies, the \$1/\omega\$ term makes the gain shrink, so high frequencies noises and sharp edges are filtered out.


• The cutoff frequency of the amplifier is at $$ \omega R_1 C = 1 \implies \omega = \frac{1}{R_1 C} $$ which is fairly high, since \$C\$ is small.

Finally (thanks to LvW), if your circuit is ringing, this capacitor adds an extra pole in the amplifier's frequency response, which can increase the phase margin and make the circuit more stable. This is a bit more complex and depends on the properties of the op-amp, so I won't go into detail.

voltage - Flipping a signal

I've an input of two input lines, one being connected to ground and one carrying the signal (measured to ground). The output should be three lines with one being ground and the others measured in respect to ground. There should be two possible uses:

1. Input is 0V output should be -0.4V and 0.4V


2. Input is 5V output should be 0.4V and -0.4V

An output current of just 10-15 µA is enough. Input can be up to 40mA (however if needed, supply voltage outside these ranges can be supplied). Can you please give me any hints?

FPGAs or CPLDs for "Glue Logic" and Video/LCD Capabilities

Some of you may remember I posted a question in which it was suggested that I use CPLDs instead of a large number of multiplexers. Here is the question, for reference.

However, as I read and learn about CPLDs and FPGAs, I realized that FPGAs are also used for video capabilities. My project is going to need something like a 6" to 7" Color LCD in any case. Note, 24 bit color or such is not required. Even an 8-bit display is more than enough for this application. But I cannot help and wonder - would it not be better that I used an FPGA instead of CPLDs? This would mean less chips to work and it will get rid of a microcontroller, possibly.

With my limited knowledge, the reasons that FPGAs don't seem like a good solution are:

1. Are likely more expensive than CPLDs.



2. A mid-range FPGA might not be handle all the logic required for the application, along with video. This implies that I may need more than one chip. At this stage, a relatively powerful microcontroller and CPLDs become more attractive. The CPLDs can be configured for all the logic required and the controller can be the brains.


3. FPGAs will require a programmer onboard as they cannot retain their programming. In comparison, CPLDs are instant-on.

Why do they seem like a good option:

1. Can possibly replace several CPLDs and micro controller.


2. More support available for FPGAs than CPLDs.

Note that I cannot use a powerful FPGA for two reasons. They are very costly and secondly, they most probably come in BGA packages. The local manufactures are able to handle BGAs but its not recommended (I asked).

Answer

1. 
   

   FPGA's are more expensive than CPLD's, but they can do so much more too. I only use CPLD's where the "instant on" (i.e., no programming time) is required, or when I need something that costs less than US$5 per chip. For everything else, an FPGA is preferable over a CPLD-- in my opinion.

   
   


2. 
   

   Rarely does it make sense to put a CPU INSIDE the FPGA. When it comes to bang for the buck, you just can't compete with an off the shelf ARM or something similar. The only times it makes sense is when you only need a tiny 8-bit micro (a.la. Xilinx Picoblaze), or you are using an FPGA that includes a hard core and space is more important than cost. For your application, you'll need a reasonable 32-bit CPU to render the graphics for the LCD. So, at the very least, you'll have a 2-chip solution (CPU + FPGA/CPLD).

   
   


3. 
   

   Yes, FPGA's need to be programmed at power-up. This can be a good or bad thing. It's bad because it means that at the very least you need a small Flash EEPROM chip that they "boot" from. It is good because it means that you can easily do "in the field firmware upgrades". With a CPLD, you'd have to drag out the CPLD programmer hardware/software every time you need to do an upgrade.

   
   

For most of the boards I've designed, I've always had a CPU that took care of programming the FPGA. That CPU has been Power-PC's, ARM's, and an Intel Atom. Since that CPU already had Flash, RAM, Ethernet, and Linux it was a piece of cake to implement the FPGA drivers and FPGA programming stuff.

In your case, I would lean toward CPLD's rather than FPGA's. Here's why:

1. 
   

   Implementing a video output circuitry in an FPGA is not trivial. If I were assigning that task to an engineer, I would not assign it to a Junior engineer. It would have to be a Sr. engineer with 10+ years of experience. A Jr engineer might be able to "make it work", but it wouldn't be very good. Since you need a 32-bit CPU anyway, you might as well get one with a video output-- like some T.I. ARM's have, as well as the Freescale iMX stuff.

   
   


2. 
   

   For those big shift registers, you need very little logic and a lot of I/O pins. More specifically, you need about 4 Flip-Flops per I/O pin. A medium sized FPGA will have maybe 300 I/O pins, but 50,000+ Flip-Flops. So you are really paying money for things you will never use. In the end, I think that you will spend about double or triple for an FPGA solution than a CPLD solution.

   
   



3. 
   

   For someone who is just starting out with programmable logic, CPLD's have a much easier learning curve. There is no sense in making things more complicated before you have to.

   
   

And here is another bit of unsolicited advise: Stick with the big FPGA/CPLD people (Xilinx and Altera). Avoid the 2nd and 3rd tier manufacturers like Lattice, Actel, Quicklogic, etc. The big guys are no more expensive (or not significantly so), their tools and support are better (and free!), and the skills you learn will be easier to use on future projects. And most importantly, it will look better on a resume!

debounce - Debouncing buttons

I recently read an article about button debouncing and was wondering if I should keep this in mind when working with, for example, an Arduino (ATMega mC)? I assume it is an issue, especially when working with interrupts.

So is it better to detect bounce in code, or should this be taken care of with hardware? Please elaborate.

Answer

I would highly recommend hooking a scope (hopefully you have one or can get your hands on one to use) up to your switch. I have seen a student's project that had a bounce on their switch that went from 5v down to -5v up to 4v down to -3v then up to 2v then back down to 0v. When we looked at the current draw on a scope there were some a very very large spike.

In his particular case it was very very much needed for him to debounce his switch in hardware.

However, on the other hand, I have seen switches that have a much smaller effect that could easily just be removed in software.

You do need to weigh your options though. If you have a very complex amount of firmware, adding the overhead on both you as a programmer and the cpu usage may not be worth it and you would be better off to just add a little bit of hardware. Now on the other hand, if you are trying to get costs and size down, you will want to remove as much hardware as possible and do it all in firmware if you can.

Common emitter circuit - can't understand negative feedback

I have a problem with understanding how does the negative feedback of this circuit work.

In all books that I read it is said that "with the rise of temperature, collector current increases". Why is that? I know that \$\beta\$ increases as well and \$U_{BE}\$ decreases. Looking at the Thevenin's configuration of \$R_1\$ and \$R_2\$:

We can write that base's potential (in Polish word for 'shunt' starts with b, so don't mind index at the image above)

\$V_B=E_s-I_BR_S=U_{CC}\cdot\frac{R_2}{R_1+R_2}-I_B\cdot\frac{R_1\cdot R_2}{R_1+R_2}\$

Hence, \$U_{BE}=V_B-V_E=U_{CC}\cdot\frac{R_2}{R_1+R_2}-I_B\cdot\frac{R_1\cdot R_2}{R_1+R_2}-I_ER_E\$

Now assume, that the temperature had increased. This means that \$U_{BE}\$ will decrease and \$\beta\$ will increase. What I don't understand is how the thought process goes next.

Answer

Assuming \$V_\text{TH}=V_\text{CC}\frac{R_2}{R_1+R_2}\$ and \$R_\text{TH}=\frac{R_1\cdot R_2}{R_1+R_2}\$, then:

$$I_\text{C}=\beta\cdot\frac{V_\text{TH}-V_\text{BE}}{R_\text{TH}+\left(\beta+1\right)R_\text{E}}=\frac{V_\text{TH}-V_\text{BE}}{\frac{R_\text{TH}}{\beta}+\frac{\beta+1}{\beta}R_\text{E}}\approx\frac{V_\text{TH}-V_\text{BE}}{R_\text{E}+\frac{R_\text{TH}}{\beta}} $$

There are two temperature-dependent variables in the above: \$V_\text{BE}\$ and \$\beta\$. As you point out, temperature tends to decrease \$V_\text{BE}\$ and increase \$\beta\$. Ignoring \$\beta\$, a decreasing \$V_\text{BE}\$ would tend to increase \$I_\text{C}\$. Ignoring \$V_\text{BE}\$ , an increasing \$\beta\$ would also tend to increase \$I_\text{C}\$. So the effects of temperature on \$V_\text{BE}\$ and \$\beta\$ tend to operate in the same direction on \$I_\text{C}\$.

As a side note, you can see that if \$R_\text{E}\gg \frac{R_\text{TH}}{\beta}\$ then this fact alone tends to stabilize the collector current against variations in \$\beta\$ (for temperature or for part variations.) \$R_\text{E}\$ also reduces variations due to \$V_\text{BE}\$, but it also simply reduces \$I_\text{C}\$, generally, too.

---

A more mathematical way of asking this question is to compare the impacts. For any given value of \$R_\text{E}\$, what percent variation in \$I_\text{C}\$ can we expect for a given percent variation in \$V_\text{BE}\$ or for a given percent variation in \$\beta\$. And knowing that, how do they compare with each other?

Here they are:

$$\begin{align*}\frac{I_\text{C}\: \text{% change}}{V_\text{BE}\: \text{% change}}&\left\{\begin{array}{l} \mu_\text{vbe}=\frac{\frac{\text{d}I_\text{C}}{I_\text{C}}}{\frac{\text{d}V_\text{BE}}{V_\text{BE}}}&=-\beta\cdot\frac{V_\text{BE}}{I_\text{C}\left(R_\text{TH}+\left(\beta+1\right)R_\text{E}\right)}\end{array}\right.\\\\\frac{I_\text{C}\: \text{% change}}{\beta\: \text{% change}}&\left\{\begin{array}{l} \mu_\beta=\frac{\frac{\text{d}I_\text{C}}{I_\text{C}}}{\frac{\text{d}\beta}{\beta}}&=\beta\cdot\frac{\left(V_\text{TH}-V_\text{BE}\right)\bigg[\frac{R_\text{TH}+R_\text{E}}{R_\text{TH}+\left(\beta+1\right)R_\text{E}}\bigg]}{I_\text{C}\left(R_\text{TH}+\left(\beta+1\right)R_\text{E}\right)}\end{array}\right.\end{align*}$$

To use them, just use them as in \$\% I_\text{C}=\mu_\text{vbe}\cdot \%V_\text{BE}\$ and \$\% I_\text{C}=\mu_\beta\cdot \%\beta\$.

For example, in one circuit I tested that was designed for \$I_\text{C}\approx 1\:\text{mA}\$ gave an actual \$I_\text{C}=1.04\:\text{mA}\$. After a \$25\:^\circ\text{C}\$ rise (using a controlled hot plate), I measured \$I_\text{C}=1.10\:\text{mA}\$. I also measured a \$-6\%\$ change in \$V_\text{BE}\$ and a \$+12\%\$ change in \$\beta\$. The above equations for the circuit I had gave me \$\mu_\text{vbe}\cdot \%V_\text{BE}=+5.8\%\$ and \$\mu_\beta\cdot \%\beta=+0.7\%\$. Combined, this suggests \$6.5\%\$ change on \$I_\text{C}\$. So:

$$I_\text{C}=1.065\cdot 1.04\:\text{mA}\approx1.11\:\text{mA}$$

Note that this is very close to what I actually got.

The ratio of the above two factors is:

$$\bigg\lvert{\frac{\mu_\text{vbe}}{\mu_\beta}}\bigg\rvert=\frac{1}{\frac{V_\text{TH}}{V_\text{BE}}-1}\cdot\frac{R_\text{TH}+\left(\beta+1\right)R_\text{E}}{R_\text{TH}+R_\text{E}}$$

Now, here you can see why \$\mu_\text{vbe}\$ dominates \$\mu_\beta\$. So long as \$V_\text{TH}\gt 2\:V_\text{BE}\$, the first factor will be somewhat less than 1. But the second factor is always greater than 1 and often a lot greater -- for example, 10 or so. So it's generally the case that with emitter degeneration in the well-designed CE circuit, the percent changes in \$V_\text{BE}\$ are more important than percent changes in \$\beta\$, even though the actual percent changes might be smaller. Their relative impacts are such that the base-emitter voltage changes are still the more important ones to worry about (if you need to worry at all.)