I'm looking for succinct yet correct guidelines for evaluating a DDR3 memory PCB layout. I know that trace length matching, via style and back-drilling, and signal grouping all matter. I know that each group of 8 data bits plus two associated control lines need to be length matched.
I'm seeking a good summary of all the issues, or people's experience, especially if it covers both multi-chip modules and single point to point (one CPU and one memory chip) layout. How critical is all this stuff for small single board CPU's?
I have read DDR1 Layout Considerations - DOs and DONTs and Compensating for unbalanced via count in DDR3 routing
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