arm - DDR3 routing: swapping data wires

Is it possible to swap wires in data bus between CPU and DDR3 x16 memory for routing optimization?

So, for data lines depends on the correct order?

For example connect DQ0 on CPU to DQ1 on memory and DQ1 on CPU to DQ0 on memory.

Personally I think that this is possible, but I'm not sure.

(About address wires it is clear that they cannot be swapped, because address bus is used also as command)

Answer

Allowed bit and byte swapping for DDR2 and DDR3:

• Within a byte, DQ signals can be swapped


• Bytes can be swapped (all signals DQ, DQS, DM have to be swapped)


• DQ signal should not be swapped between bytes (e.g. DQ0 going into DQS2 group)

Also all command and adress signals must not be swapped.

LPDDR2 feature a mode register functionnality but it seems that nobody use this. Nevertheless if you want to be able to use it, first data byte should be routed straight. On DDR3 the mode register function is use through address bus, so you don't have to worry.

Finally some memory controller require some pins to be fixed for example with Freescale i.MX6. So read datasheet and application notes of your memory controller to be sure what you are allowed to and don't hesitate to contact the manufacturer.

Further reading: https://forums.xilinx.com/t5/Memory-Interfaces/possible-to-swap-pin-at-DDR3-memory-side/td-p/164558