I'm using an external 20MHz (categorized as high-speed or HS range) resonator and using PLL, but I'm not able to clock the device up anywhere near the max cpu speed advertised. How are you ever supposed to achieve 120MHz for F_SYS?
See section 7.7: Phase-Locked Loop, p.7-23:
Constraints:
- 0.8 MHz ≤ F_PLLI ≤ 8.0 MHz
- 120 MHz ≤ F_OSC ≤ 340 MHz
- 15 MHz ≤ F_SYS ≤ 120 MHz @ 125ºC
Equations:
- \$F_{PLLI} = \dfrac{F_{IN}}{(PLLPRE + 2)}\$
- \$F_{OSC} = F_{IN} \cdot \dfrac{(PLLDIV + 2)}{(PLLPRE + 2)}\$
- \$F_{SYS} = F_{IN} \cdot \dfrac{(PLLDIV + 2)}{((PLLPRE + 2) \cdot 2 (PLLPOST + 2))}\$
If you can get to 340MHz, the highest you can go is if PLLPOST = 0: 340MHz / (2 * (0 + 2)) => 85MHz!
Answer
You appear to have your \$F_{SYS}\$ and \$F_{OSC}\$ formulae mixed up, per the datasheet you cited.
- \$F_{SYS} = F_{IN} \cdot \dfrac{(PLLDIV + 2)}{(PLLPRE + 2)}\$
- \$F_{OSC} = F_{IN} \cdot \dfrac{(PLLDIV + 2)}{((PLLPRE + 2) \cdot 2 (PLLPOST + 1))}\$
By my math, with a 20MHz crystal and the following settings, you should get 240MHz at \$F_{SYS}\$ and 120MHz at \$F_{OSC}\$:
- PLLPRE: 4
- PLLDIV: 70
- PLLPOST: 0
\$F_{SYS} = 20MHz \cdot \dfrac{72}{6} = 240MHz\$
\$F_{OSC} = 20MHz \cdot \dfrac{72}{(6 \cdot 2)} = 20MHz \cdot \dfrac{72}{12} = 120MHz\$
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