Proper (low power) use of a tri-state buffer when used as level shifter.

In my application, I have a 3.3v MCU driving a logic line based device at 4-5V where I need to be able to put the level shifter in a high impedance state. (This is particularly important to avoid current backflow with the badly designed chips I'm using.) Following advice from this answer, I sourced a NXP 74LVC2G125.

For the Tri-state buffer, I am driving VCC at 5 volts, but the OE and inputs using 3.3V logic. As I read the data sheet, these are acceptable ranges for logic input HIGH. However, I notice in practice that when the OE is pulled high (to 3.3V) to shut down the tri-state buffer, the chip continues to consume about 10mA. This suggests to me that despite the specifications, I am not saturating whatever transistor is driving the high impedance state. I am aiming for a low-power application.

I'm looking for a replacement chip that will serve the same purpose. What specification should I look for to be sure the 3.3V logic will completely shut down and fully activate the tri-state buffer? For instance, will this same chip SN74LVC2G125 from TI have the same problem? Or will a variation on the chip, such as SN74LVC2G241, address the issue?

I do not have any analog EE background.

Answer

As another answer already said, 3.3 V is not sufficient to guarantee fully switching a CMOS gate powered by 5 V.

You should consider swapping your LVC part for one from one of the "T" logic families like HCT or ACT.

These have TTL input levels, so that 3 V is guaranteed to fully switch the inputs, but provide full swing output levels like CMOS families.

For example, 74HCT125 provides four independently-enabled non-inverting buffers with these logic properties. 74AHCT125 does the same, but with lower quiescent current, and probably other spec changes.