flipflop - JK flip flop random start outputs

I am working on a project for college and I have to implement a sort of alarm using only MUX's and JK flip flops and a bread board. The problem I encountered is that whenever I power the whole circuit my flip flops have random outputs. I have 2 SN74HC73's meaning I have 4 flip flops. I connected all ports(correctly, checked three times) and have CLR set to HIGH (basically connect it to the power source) for all 4.

Is there a way to ensure that all flip flops default to 0 once I power the circuit on?

Please help me :)

Answer

There is nothing in the specifications, nor in the internal schematics, that defines what the outputs of a JK flip-flop should be at power-on. The only way of getting a known state is to use the CLR input of the chip, which resets the whole chip into a known state.

The normal way of doing this is to hold CLR low for a short period while the chip powers up, and only then release it to HIGH. The simplest way to do this is with a capacitor and resistor on the pin.

^{simulate this circuit – Schematic created using CircuitLab}

You will need to experiment to get the component values right for your situation. The larger the values the slower the capacitor will charge, and the longer the delay before the CLR pin goes high. R2 acts as a "bleed" resistor to remove the charge from the capacitor ready for the next power-on. It should be much higher than the charge resistor R1 as the two of them act like a voltage divider defining the maximum level of the capacitor's charge. It may or may not be needed depending on the self-discharge of the capacitor and leakage current of the CLR pin when VCC is removed.