fpga - When is VHDL code considdered compile time

EDIT:

I am working with a lookup table which is generated in compile time.

Is this compile time code:

• 
  

  because sinus_table is a constant

  
  


• 
  
  

  or because any computation before begin is compile time.

  
  

Or maybe both?

ARCHITECTURE Behavioral OF set_output IS

----------------------------------------------------------------------
-- Begin - Generate the lookup table
------------------------------------------------------------------------


  -- Elements per Signal
  CONSTANT table_length : integer := 2**sinus_width;

  IMPURE FUNCTION createSamples RETURN output_sinus IS
    VARIABLE result : output_sinus(0 TO table_length - 1);
    VARIABLE table_step : real := 2.0 * math_pi / real(table_length);
    VARIABLE sinus_result : real;
  BEGIN
    FOR i IN 0 TO table_length - 1 LOOP
      sinus_result := sin((real(i)) * table_step) / 2.0;

      result(i) := std_logic_vector(to_signed(integer(sinus_result * real(table_length - 1)), sinus_width));
    END LOOP;
    RETURN result;
  END FUNCTION createSamples;

  CONSTANT sinus_table : output_sinus := createSamples;

------------------------------------------------------------------------
-- End - Generate the lookup table
------------------------------------------------------------------------

------------------------------------------------------------------------
-- Begin - Manage the address and return the sine wave
------------------------------------------------------------------------

BEGIN

PS: Do you know of any literature that I can cite about this?

(Most of the literature that I found explains synthesis/elaboration)...