flipflop - Understanding max and min propagation delay in flip-flops

I've been working my way through Digital Design and Computer Architecture, but am very confused by the equations for time delay - what each of the variables are, and how to conceptualize these equations.

Assuming no clock skew, the book gives the following two formulae:

$$t_{pd} \le T_c - (t_{pcq} + t_{setup})$$

$$t_{cd} \ge t_{hold} - t_{ccq}$$

What I understand so far is that contamination delay is the minimum amount of time that will pass before an inputted value will start to change, and the propagation delay is the maximum amount of time that will pass before the output is sure to be resolved. I also understand that the setup time is the amount of time before the rising edge of the clock that an input must have stabilized, and the hold time is the amount of time after the edge that we wait before we can be certain that the output is stable.

Assuming this understanding and no further, can you please explain and help me conceptualize the two above equations?

Answer

The first equation tells you the maximum propagation delay allowable through a block of combinational logic between two clocked registers. For ideal flip-flops the delay would just be the clock period, \$T_C\$, but for real flip-flops you have to subtract the time from the clock edge until the inputs of the combinational block (the outputs of the first set of flip-flops) become stable, \$t_{PCQ}\$, and the required setup time (when the outputs of the combinational block must be stable before the clock edge on the second set of flip-flops), \$t_{setup}\$.

The other side of the timing analysis is that the flip-flop inputs must remain stable for a short period of time after the clock edge to make sure that the inputs are properly latched. This characteristic of a flip-flop is called the hold time, \$t_{hold}\$. In order to satisfy the second flip-flop's hold time requirement, it is necessary that the clock-to-q contamination delay, \$t_{ccq}\$, plus the contamination delay of the combinational logic, \$t_{cd}\$, must be greater than the flip-flops hold time requirement. Rearranging the equation, you can specify the relationship between a characteristic of the combinational logic, \$t_{cd}\$, to the two characteristics of the flip-flops, \$t_{hold}\$ and \$t_{ccd}\$.

In practice, you will have many combinational paths in a block of logic between two sets of registers. For the first equation you should use the largest propagation delay of any path, while for the second you should use the smallest contamination delay on any path.