Tuesday 29 April 2014

pcb design - Do chips really need multiple values of decoupling capacitor in the same packages?


A similar question is asked here: "two bypass/decoupling capacitors" rule? But that question was about parallel bypass capacitors without mentioning package size (but the answers mostly assumed paralleling parts with different package sizes), while this one is specifically about parallel bypass capacitors in the same package size.





I recently attended a course on High speed digital design, where the lecturer went to some length to explain that a capacitor's performance for decoupling was limited almost entirely by its inductance, which in turn was almost entirely due to its size and placement.


His explanation seems to clash with the advice given in many datasheets, which suggest multiple values of decoupling capacitor even though they have the same package size.


I believe his recommendation would be: for each package size, choose the highest capacitance that's feasible, and place it as close as possible, with smaller packages closest.


For example, in a schematic from Lattice Semiconductor, they suggest the following:



  • 470pF 0201

  • 10nF 0201

  • 1uf 0306



Multiple decoupling capacitors


Q1: Is that 470pF capacitor really helping?


Q2: Wouldn't it make sense to replace all three of them with a single 1uF capacitor in an 0201 package?


Q3: When people say that a higher value capacitor is less useful at higher frequencies, how much of that is due to the capacitance, and how much is due to the increased package size usually associated with larger caps?




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