fpga - MUX verilog code

Can anyone explain the difference between the two codes below. Both written in Verilog, Xilinx. If someone can explain how the second one works would much appreciate it.

module decoder_24(in1, in2, out1, out2, out3, out4);
    input in1,in2;
    output out1,out2,out3,out4;
    assign  out1 =!(!in2&!in1);
    assign  out2 =!(!in2&in1);
    assign  out3 =!(in2&!in1);
    assign  out4 =!(in2&in1);
endmodule


module multiplexer41_4bit(input0, input1, input2, input3, sel0, sel1, out);
    input [3:0] input0,input1,input2,input3;
    input sel0,sel1;
    output [3:0] out;

    //multiplexer0
    multiplexer_41 M41_0(input0[0],input1[0],input2[0],input3[0],sel0,sel1,out[0]);

    //multiplexer1

    multiplexer_41 M41_1(input0[1],input1[1],input2[1],input3[1],sel0,sel1,out[1]);

    //multiplexer2
    multiplexer_41 M41_2(input0[2],input1[2],input2[2],input3[2],sel0,sel1,out[2]);

    //multiplexer0
    multiplexer_41 M41_3(input0[3],input1[3],input2[3],input3[3],sel0,sel1,out[3]);
endmodule

Second:

case({m_sel2,m_sel1})
    2'b00: m_out = m_in1;   
    2'b01: m_out = m_in2;
    2'b10: m_out = m_in3;    
    2'b11: m_out = m_in4;   
    default: m_out = 1'b0;
endcase