fpga - Does setting pins as virtual affect timing?

I have a Verilog submodule which I am testing independently. This module has too many top level pins to fit in my FPGA, so I have set some of the pins as virtual so that it would compile without optimizing away the corresponding signals.

I am however concerned that the timing analysis is affected by setting those pins as virtual. I have a feeling that the pins are effectively false pathed.

Does setting top level pins as virtual in Quartus II affect timing? If so, how can I make sure that the timing analysis is as if the FPGA had enough pins to start with?

Answer

I just finished a project at the customer site mapping an IP with over 2700 IOs. In the first steps the project, we used a wrapper to put all the signals into a giant shift register to make sure they were not optimized. But later on we used the Virtual IOs to get the timing of the design correct and get the right estimate of the needed resources for the project.

Using Virtual IO, in my experience does not affect the timing of your design. You can "FALSE PATH" those signals if you want, but if you don't and those signals are connected to one of your clocks, then you will get the proper timing analysis of those signals.