$random in Verilog doesn't seem to be working

In Verilog, $random generates different random inputs but this doesn't seem to be working when I try. Each time I use $random for a reg or integer, I must be getting different different values but that is not so. I tried it even in Modelsim simulator.

http://www.edaplayground.com/x/Umt

`timescale 1ns/1ns
module tt;
integer kk;


initial
begin
  repeat(5) begin
    kk=$random % 10;
  end
  $monitor("%d",kk);
end
endmodule