parallel - Implementation of AES algorithm using Systolic architecture

I need to generate a VLSI Systolic array to implement the AES encryption algorithm with key length of 128 bits. Following are the possible ways :

1. Systolic for Key expansion


2. Systolic in MixColumn


3. Systolic for the on-the-fly calculation of S-box

For option #3, I am referring to this paper. Figure 2.1 from this paper gives the steps for calculating multiplicative inverse, which is the first step in S-box calculation. I am trying to convert this diagram into a systolic array, but haven't reached a concrete solution until now.

I am also referring to this paper to convert a cyclic algorithm into a Systolic one. However, I am not able to convert the operations involved in the AES encryption into Systolic structure. Could anyone give me any pointers on how to approach this problem?