Scaling an input in VHDL

I want to attenuate an incoming signal (16 bit signed number between -1 and 1) by a certain amount (let's say 0.8), i.e.,

incoming = incoming * 0.8

Where incoming is a signal:

signal incoming : std_logic_vector(15 downto 0);

But I'm having trouble getting this to work. Inside a process block:

variable temp : std_logic_vector(31 downto 0);
variable scale_factor : std_logic_vector(15 downto 0) := x"6666";

begin

incoming_raw <= data_in;

temp := incoming_raw * scale_factor;
incoming <= temp(31 downto 16);

end process;

ModelSim doesn't like this and gives me:

# ** Error: /home/blah/blah.vhd(254): No feasible entries for infix operator "*".
# ** Error: /home/blah/blah.vhd(254): Bad right hand side (infix expression) in variable assignment.

Why can't the * operator do this when both operands are 16 bit std_logic_vectors?