Corner Cases to Verify Synchronous FIFO

I'm trying to figure out the corner cases for verifying a synchronous FIFO during hardware verification.

My setup is a very simple two ports synchronous FIFO (write/read) and the write clk frequency is same as read clk frequency.

In order to test whether the FIFO overflow occurs or not, can somebody help me identify those corner cases so that we can completely verify this simple synchronous FIFO?