FPGA Jtag Hooking to User Logic

After some primer reading on jtag it looks to be a nifty means to test a FPGA logic design in a consistent and sustainable way.

Let's use altera max 10 as an example. I've read this MAX 10 JTAG Boundary-Scan Testing User Guide. My reading is, to be able to access the user logic the jtag tester (a host pc most likely) will send USER0 or USER1 instructions.

Questions are:

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  How do you implement some logic in the user logic design to catch the commands and parameters, and return some results? Examples?

  
  


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  On the host, how do you send those commands, preferably with a low-cost or open-source tool? With some experience, I know Olimex produces some good jtag adapters, and also altera usb blaster is a popular tool. Openocd may be a popular software candidate.

  
  
  

It will be great if somebody can shed lights on any part of the questions.