I have a slight problem with my clock domain crossing timing constraints.
I have two clock groups
set_clock_groups -asynchronous -group {clk_A} -group {clk_B}
As I understand it this will cause all signals from clk_A
to clk_B
to be treated as false paths.
However I would like to constrain a few of these paths as
set_max_delay -to [get_registers {*|*|some_reg}] 8
But if I understood the Altera documentation correctly. The implicit false paths created from the asynchronous clock groups will cause the later constrain to be ignored.
For now it beats my why a more specific constrain has less priority then the more general one.
Has anyone solved this in a practical fashion, or do I need to stop using clock groups and constrain all relevant paths manually?
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