verilog - Can an FPGA design be mostly (or completely) asynchronous?

We had a very short FPGA/Verilog course at university (5 years ago), and we always used clocks everywhere.

I am now starting out with FPGAs again as a hobby, and I can't help but wonder about those clocks. Are they absolutely required, or can an FPGA-based design be completely asynchronous? Can one build a complex bunch of logic and have stuff ripple through it as fast as it can?

I realise that there are a whole lot of gotchas with this, like knowing when the signal has propagated through all parts of the circuit and the output has stabilised. That's beside the point. It's not that I want to actually build a design that's entirely asynchronous, but just to improve my understanding of the capabilities.

To my beginner eye, it appears that the only construct that absolutely requires a clock is a reg, and my understanding is that a typical FPGA (say, a Cyclone II) will have its flip-flops pre-wired to specific clock signals. Is this correct? Are there any other implicit clocks like this and can they typically be manually driven by the design?

Answer

A short answer would be: yes; a longer answer would be: it is not worth your time.

An FPGA itself can run a completely asynchronous design no problem. The result you get is the problem since timing through any FPGA is not very predictable. The bigger problem is the fact that your timing and resultant design will almost definitely vary between different place and route sessions. You can put in constraints on individual asynchronous paths making sure that they do not take too long, but I'm not quite sure that you can specify a minimum delay.

In the end it means that your design will be unpredictable and potentially completely variable with even a slight design change. You'd have to look through the entire timing report every time you change anything at all just to make sure that it would still work. On the other hand, if the design is synchronous, you just look for a pass or fail at the end of place and route (assuming your constraints are setup properly, which doesn't take long at all).

In practice people aim for completely synchronous designs but if you need to simply buffer or invert a signal, you don't need to go through a flip flop as long as you constrain it properly.

Hope this clears it up a bit.