I have been seeing these switched capacitor circuits for some time now and have even seen Z-transform being used to model how these circuits behave. While I can see that there is some capacitor that switches, what exactly is the mystery behind this 3 terminal device one terminal of which comes from some sort of clock. How is this clock generated?
I am wondering how do these things work from within a circuit but don't know how to get a good thorough answer.
Answer
Switched cap circuits are typically used in chip design because it's far far easier to get small, high value caps that match each other than it is to get resistors that meet all those same criteria. Until there was a need the circuit technology and theory wasn't developed, once circuits got smaller the need arose and bingo! it appeared.
The relationship between resistance and capacitance in a switched cap circuit is:
\$R_{equ}=\dfrac{1}{Cf_{clk}}\$
If I want to emulate a \$10M\Omega\$ resistor I can do it with a \$0.5pF\$ cap and two switches running at \$200 kHz\$. the switches can be a CMOS transmission gate of 1 PMOS and 1 NMOS. This might take up \$0.001 mm^2\$ in a \$0.5 \mu m\$ process. In comparison a \$10 M\Omega\$ diffused resistor in the same process might take \$ 1.0 mm^2\$. This is a factor of ~\$1000\$.
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