fpga - Spartan 6 DCM unstable clock output

Spartan 6 clocking resources. The link here refers to the clocking resources of spartan-6 FPGA. I am using the DCM-CLKGEN primitive described in the link, to generate a 8x clock based on an input clock. It works fine as long as the input clock is stable.

But now i sweep the input clock at every 90 us by ±5%. I see that although the DCM does not lose lock, it takes very long (15 to 20 us) to change the output freq after changing the input frequency. This is for me undesirable. Any suggestions?

This question was posted on the xilinx forum and the suggestion was to reset the DCM everytime it loses lock. But the problem is that the DCM is not losing lock

Also, this was earlier posted on stackoverflow and now has been reposted here.