Friday, 29 March 2019

components - Where are the depletion PMOS transistors?


In school, I was taught about PMOS and NMOS transistors, and about enhancement- and depletion-mode transistors. Here's the short version of what I understand:


Enhancement means that the channel is normally-closed. Depletion means the channel is normally-open.


NMOS means the channel is made of free electrons. PMOS means the channel is made of free holes.


Enhancement NMOS: positive gate voltage attracts electrons, opening the channel.
Enhancement PMOS: negative gate voltage attracts holes, opening the channel.
Depletion NMOS: negative gate voltage repels electrons, closing the channel.
Depletion PMOS: positive gate voltage repels holes, closing the channel.


It's been six years since I started doing design work for a living, and on at least one occasion I've wanted (or at least thought I wanted) a depletion PMOS transistor. It seemed like a good idea for a bootstrap circuit for a power supply, for example. Yet no such devices seem to exist.


Why are there no depletion PMOS transistors? Is my understanding of them flawed? Are they useless? Impossible to build? So expensive to build that a cheaper combination of other transistors is preferred? Or are they out there and I just don't know where to look?




Answer



Wiki says...


In a depletion-mode MOSFET, the device is normally ON at zero gate–source voltage. Such devices are used as load "resistors" in logic circuits (in depletion-load NMOS logic, for example). For N-type depletion-load devices, the threshold voltage might be about –3 V, so it could be turned off by pulling the gate 3 V negative (the drain, by comparison, is more positive than the source in NMOS). In PMOS, the polarities are reversed.


So for a depletion-mode PMOS it is normally ON at Zero volts but you need 3V or more on the gate higher than the supply voltage to turn OFF. Where do you get that voltage? I think , that's why it is uncommon.


In practise now we call them High Side Switches or Low Side switches for power MOSFETs. They prefer not to combine enhancement and depletion mode in the same chip as the processing costs are almost double. This patent defines some innovation and better physical desc. than I can remember. http://www.google.com/patents/US20100044796


It is possible though what you are suggesting and performance are key issues. However when it comes down to low ESR, MOSFETS are like voltage controlled switches with ESR changing over a wide range of DC voltages unlike bipolar transistors which are 0.6 to < 2V for max peak in some case. Also for MOSFETs it is constructive to think of them as having an impedance gain of 50 to 100 when looking at loads and ESR of source. So consider you need a 100 ohm source to drive 1 ohm MOSFET and 10 ohm source to drive a 10mΩ MOSFET if you use 100:1, Conservative is 50:1. This is ONLY important during the transition period of the switch, not the steady state gate current.


Whereas bipolar hFE drops dramatically so you consider hFe of 10 to 20 good when saturated for a power switch.


Also consider that MOSFETS as charge-controlled switches during transition, so you want to have a big charge available to drive the gate capacitance and load reflected into gate with a low ESR gate drive, if you to make a fast transition and avoid commutation ringing or bridge cross-over shorts. But that depends on design needs.


Hope that isn't too much info and the patent explains how it works for all modes of P N type depletion and enhancement in terms of device physics.


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