Today I learned about the concept of memory training for DDR2, 3, and 4 (I'm not sure if DDR1 has it). The purpose of memory training is to correct for skew in data, address, and command bits being sent between controller and memory (presumably using a programmable analog delay?).
Also important for DDR is the concept of length matching, to ensure that each bit in a given word in DDR arrives to the DRAM/to the controller within a clock period. This is to ensure the data receiver "sees" the correct bit pattern when it's time to latch.
These seem to be accomplishing the same task. Clearly, I can look at any board with DDR memory and see length-matched traces, but it leaves me wondering: What physical, technical, or business decisions make it impractical for a DDR(2-4) controller itself to compensate for skew due to mismatched lengths, as long as the incoming clock is skewed as well to after what the controller determines is the latest-arriving bit?
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