digital logic - In a JK Binary Counter from 0 to 9, why is the NAND gate connected to the second and fourth J-K flip flop and not the first and fourth?

In a binary counter design using 4 J-K flip-flops, that counts from 0 to 9, the flip flops are reset when the output from the 2nd flip flop NAND the 4th flipflop equals to 0. Since binary 9 is 1001, why is the NAND connected to these 2 outputs and not the first and fourth since it's the first and fourth bits that are 1s.