Monday, 1 October 2018

fpga - System Generator: How to configure the CORDIC divider block?


He all, I was wondering how should be the parameters fo the CORDIC divider block in order to get proper results. In this example I´m trying to get 0.1/0.2 = 0.5 but I don´t get it and I don´t know why? Please, does anyone know how to do it? Thank you!!!


EDIT: To take a look to the parameters of the CORDIC block see this question: System Generator: How to configure the CORDIC divider block. Understanding the block parameters


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Answer



From the latency on the cordic block, that looks as if you've chosen to use a single processing element - that will produce results of limited accuracy. Very limited it appears :)


I tried using 10 elements for example, with [zeros (1,9) 1] for the "latency per processing element" - to get back to your 21 tick latency. Making sure I ran the simulation long enough (oops), I then got a result (using UFixed_16_11 inputs) of 0.501953125. Which is closer...



Does that help?


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