Why old PMOS/NMOS logic needed multiple voltages?

Why does old PMOS/NMOS logic needed multiple voltages like +5, -5, and +12 volts? For example, old Intel 8080 processors, old DRAMs, e.t.c...

I'm interested in the causes on the physical/layout level. What was the purpose of these additional voltages?

_{Yes, this question is about stuff which was used 35 years ago.}

Answer

The 8080 used nMOS-only technology (no CMOS = pMOS and nNMOS). When you use nMOS (or pMOS) devices only, you have a couple of choices to build a logic inverter cell (see chapter 6.6 in this document, my answer borrows heavily on this source):

1. 
   
   

   nMOS transistor and pull-up resistor. Simple, but not good on an IC because the resistor would take up a lot of space on the silicon.

   
   


2. 
   

   nMOS transistor and a second, saturated nMOS transistor in place of the pull-up resistor. Not bad, but the high-level output voltage will stay one threshold voltage V_GS,th below the supply voltage. (Note: V_GS,th is the voltage between a FET's gate and source that will just turn on the FET.)

   
   


3. 
   

   nMOS transistor and a second, non-saturated (= linear) transistor in place of the pull-up resistor. High-level output voltage will swing all the way to V_DD, but this comes at the extra cost of an additional voltage V_GG with V_GG > V_DD + V_GS,th. This is the reason for the +12 V rail.

   
   


4. 
   

   nMOS transistor with a second, depletion-mode n type transistor in place of the load resistor. No additional supply rail needed, but the technology is more sophisticated because two differetly doped transistors need to be made on the same chip.

   
   
   

It seems that the 8080 uses option number 3.

The reason for the negative rail (-5 V) could be the bias needed for a cascode configuration. This would increase switching speed at the cost of an additional supply rail. I can only guess here because I have not found any sources telling me that the 8080 really uses cascode-connected stages. Covering the cascode would be another story; this configuration is used for linear amplifiers, logic switches, level-translators or power switches.