xilinx - ERROR:NgdBuild:604 using FIFO in VHDL

I would like to use a FIFO in VHDL, I used coregen to make it but when I want to use it into my project, I get this error :

ERROR:NgdBuild:604 - logical block 'U101' with type 'fifo_generator_v9_3' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'fifo_generator_v9_3' is not supported in target 'spartan3a'.

I can't find where this error come from... Here's some parts of my code (those with the FIFO) :

component fifo_generator_v9_3 is
PORT (
        M_CLK : IN STD_LOGIC;
        rst : IN STD_LOGIC;
        din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
        wr_en : IN STD_LOGIC;
        rd_en : IN STD_LOGIC;
        dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
        full : OUT STD_LOGIC;

        empty : OUT STD_LOGIC
        );
end component;


signal WRITE_EN, READ_EN, FIFO_FULL, FIFO_EMPTY : STD_LOGIC;
signal DATA_IN, DATA_OUT : STD_LOGIC_VECTOR(17 downto 0);

U101:fifo_generator_v9_3
port map (

            M_CLK,
            rst,
            DATA_IN,
            WRITE_EN,
            READ_EN,
            DATA_OUT,
            FIFO_FULL,
            FIFO_EMPTY
            );

Q : Can someone tell me where that error come from (in my case) ? Is it possible that I'm missing a file? In that case, where can I find it?

Thanks in advance !

Answer

Ok so the right answer was (as Brian Drummond said) that I needed to add the Coregen path to the search paths or I could move the fifo_generator9_3.ngc file to my project directory, I did the second one and it works !