digital logic - fpga verilog dual access

I need to write to a register from 2 sources.. in this case, a pci host and a microcontroller. The 2 will never access the register at the same time (basically once the PCI is done , it hands it over the other host, which will then have exclusive access until it's finished).

Since the clock domains are different, I can't just have multiple processes writing to the same register..

always @(posedge pciclk or negedge nrst)
   if pci_wr & pci_addr == 0
        cntl_reg = pci_data

always @(posedge mcclk or negedge nrst)
   if mc_wr & mc_addr == 0

        cntl_reg = mc_data

So how is this typically done? Not sure if this a fundamental architectural question, or just a syntax question on how to write the sensitivity list.