I have a 2-layer PCB with ADC communicating using SPI. This board is to be used with a National Instruments (NI, LabVIEW) FPGA, with a clock rate up to approximately 600kHz (higher would be nice, but this is the immediate requirement).
The board will be used near a pair of moderate-sized AC motors. When the motors are not powered, everything works fine. Once the motors are powered, I observe large amounts of electrical noise on just about everything. The communication breaks down and the data output is junk.
In case this information is useful, holding a BNC cable with two clips in the air shows voltage oscillations on the order of 500mV pk-pk; clipping these together takes it down to ~10mV pk-pk when observed using an oscilloscope.
The cabling in use is 28 AWG, 10 core (5 twisted pairs). 8 wires are signals, with a pair used for +15V and Gnd connections. Logic levels are 3.3V on the other lines. The twisted pairs aren't related, although I aimed to put the two highest frequency lines (SCLK, D_Out) with the slowest changing (essentially DC) lines to try and mitigate cross-talk.
The shields of the cabling are connected to the ground of the PCB and disconnected at the instrument end. Should this be reversed? (does it matter?) It's my understanding connecting both ends might/would lead to ground loops - is this correct, or did I completely misunderstand the principle here?
The 8 signal lines are connected to BNC lines, but the shields of the BNC cables are floating. The instrumentation specifies/expects a 50 Ohm cable. http://www.ni.com/pdf/manuals/374614a_02.pdf
How much should I be concerned about load mismatch at these frequencies? What can I do to mitigate this issue?
What should I be doing with cable grounds, connections and terminations to avoid being overwhelmed by EMI/noise?
Edit for basic drawing (even though there are 4 inputs available on the PCB for +ve, -ve PS, only two wires are available, so just one ground connection. The other can be used to connect the shield if desired): 
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