Max switching frequency of GPIO pins of modern cheap FPGA

How can we estimate maximum switching frequency of GPIO FPGA pins? What is maximum data rate achievable when connecting two FPGAs together without using of integrated high-speed transceivers? Or when we are bitbanging GPIO to VGA, what is maximum pixel clock?

I'm interested in modern cheap Altera devices, like Cyclone IV, Cyclone V (E version, not GT), and Xilinx devices like Spartan 6.

There are some figures in datasheets saying 300-400 MHz for GPIO pins, but are they real? How can we drive pin at 300-400 MHz when maximum core clock is only 100-150 MHz?