Thursday, 14 July 2016

fpga - Determine which clock has arrived first


There are two clocks of the same frequency, but one has a phase shift. So we have two clocks, one leading and one lagging. How can we determine which clock has arrived first?



One way would be to use another faster clock in the design to sample these two clocks and make a decision.


Is there any simpler way to achieve this in RTL?




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