vlsi - Why delays cannot be synthesized in Verilog?

I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code.

For example: x = #10 y; will be considered as x = y; by the synthesis tool.

What are the reasons delay declarations in any hardware description language (for example, VHDL, Verilog or Sytem-Verilog) cannot be synthesized?