fpga - UART Receiver Sampling Rate

I am trying to create a UART receiver in Verilog for my FPGA. I was following this guide http://www.fpga4fun.com/SerialInterface4.html

According to it the standard practice for asynchronous communication is to oversample the signal at 16 times the BAUD rate. This makes sense to me since I would need to do this to detect the first drop quickly and synchronize with the transmitting clock.

What I am wondering is why not just sample at the same frequency as the clock on my FPGA which is a lot fast than 16x the BAUD (my clock is 100 MHz). Is there any harm in doing this? I know it would probably just consume more power, but would it work or is there something I am missing?

Answer

I've sampled at 8 times on one job and it was OK so there is no rule dictating that 16 is the magic number so sampling higher than this is not a problem in anthing other than handling bigger numbers in hardware. Here's a the 16x counter idea: -

From the falling edge of the start bit you "find" the start-bit's "middle" by counting to 8 then, each count of 16 thereafter you "sample" the UART received data to recreate the byte (or bytes) transmitted. Clearly if you had a 32x counter you'd get a tad more accuracy in determining the centre-point of the bit and counting at a higher rate is going to work but the numbers get bigger and the power consumption rise.