I read the ATX power supply design guide, and I have a question related to the PWR_OK line specifications. In "Table 21. PWR_OK Signal Characteristics" I saw the following: "Logic level high - Between 2.4 V and 5 V output while sourcing 200 μA". My question is: what does this mean exactly? When PWR_OK is high the current will be limited by the PSU at 200 uA, so I will not be able to draw more than that from the PWR_OK line?. Or if I am trying to interface something with the PWR_OK line I should take precautions not to draw more than 200uA?
Answer
You'll most likely have to limit the current yourself. It's under that condition that the voltage is specified. Going higher than 200\$\mu\$A will probably cause the voltage to sag below 2.4V, which is the minimum for a high level in TTL. (I've also seen 2.7V as the minimum, I guess it depends on the TTL subfamily.)
Note that the same table says that "signal type = +5V TTL compatible", and that a low level is specified as < 0.4V. That output level is 0.4V less than the maximum TTL input level for a logic 0. And the 2.4V is 0.4V higher than the minimum for a high input level. This gives a 0.4V noise margin.
If you want to control a MOSFET with the PWR_OK signal, like OP, you'll need a logic level MOSFET, which draws enough current at a low \$V_{GS}\$. The BSG103 may be a good choice; it has an \$I_D\$ of 750mA at a \$V_{GS}\$ as low as 1.5V.
edit
On second thought the BSH103 may be too good. It has a \$V_{GSth}\$ of 0.4V, which means that worst case you'll have a drain current of 1mA with PWR_OK low. Even FETs with a \$V_{GSth}\$ of 1V typical indicate 0.4V as a minimum value. Can be fixed by using a resistor divider to lower the output voltage from PWR_OK. A 15k\$\Omega\$ + 25k\$\Omega\$ gives you a minimum gate voltage of 1.5V, while the current is maximum 125\$\mu\$A.
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