I want to design a finite state machine that is similar to a 3 bit counter. There are 3 bits of state (i.e. a 3 bit unsigned number) and the counter must count by 3's. More specifically, the sequence it should undergo is 0, 3, 6, 1, 4, 7, 2, 5, 0, 3, 6, 1.
I want to first produce a truth table showing what the next state of the machine should be as a function of the current state. Then I want to produce a combinational circuit using gates and D-flip flops that implements this state machine.
How do I do this?
No comments:
Post a Comment