I'm using a MOSFET to buffer my signals from a CPLD. The signals travel external to the PCB using long (from 1m to 10m) wires and then come back to the same PCB - the wires are actually the component under test. The pull up resistor, R2, is situated on the input side of the PCB. I was probing my signals when I noticed that my fall time is very fast (4.4ns fall time) yet my rise time was 264ns. Here's my schematic of the buffer:
Here are some captures from my oscilloscope:
The circuit actually works just fine. I've had a unit under long term testing and I've had zero issues so far. I am just curious what could cause asymmetrical rise/fall times. My theory is that it's because I'm using the MOSFET in open-drain configuration. The 1K pull-up resistor slows down the rising edge of the waveform and if I used a smaller resistor, the edge would rise quicker.
NOTE: Please ignore the ringing on the falling edge. I've asked a separate question regarding that.
Answer
Like Telaclavo says it's in the difference of the output drive when low versus high. When high the output sees a 1k\$\Omega\$ impedance, when low a few hundred m\$\Omega\$. This only causes the effect you're seeing if the output is capacitively loaded, if the capacitance is zero you would see the same rise and fall times. From the rise time you can even estimate the capacitance: the 99% level will be reached after about \$5 R C\$.
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