vhdl - std_logic or std_ulogic?

It seems that the world has decided that std_logic (and std_logic_vector) are the default way of representing bits in VHDL. The alternative would be std_ulogic, which is not resolved.

This surprises me because usually, you're not describing a bus, so you do you don't want multiple drivers and you don't need to resolve a signal. The advantage of std_ulogic would be that the compiler warns you early on if you have multiple drivers.

Question: is this just a cultural / historical thing, or are there still technical reasons to use std_logic?

Answer

Std_logic is a subtype of std_ulogic and has exactly one extra property: it's resolved if there are multiple drivers.

Regardless of common practice, std_ulogic is the correct type to use for non-resolved signals that need 9-valued logic. (Often, using "bit" is even more correct -- for instance, on some FPGA architectures that do not have any such thing as an 'X' or a 'U').

Basically, the best thing to do is use the correct type for the job. Often bad practices get propagated by people just parroting the style that they see others use, do without understanding why.